Arithmetic element controller

Details Arithmetic element controller Arithmetic element controller

G - Physics

06

F

354/166, 354/230

G06F 9/302 (2006.01) G06F 13/16 (2006.01)

Patent

CA 2007061

ARITHMETIC ELEMENT CONTROLLER ABSTRACT An arithmetic element controller (17) which provides for memory address generation for three independent memories of a signal processor (10) and for direct memory access from external devices by way of an interface (11). The arithmetic el- ement controller (17) comprises a first address generator (170) which includes a gen- eral purpose address generator circuit (171) and three separate address generator cir- cuits (172, 174, 175) which generate memory addresses for data store, control store and micro store memories (13, 15, 18), respectively. A second address generator (176) comprises two address generator circuits which comprise memory address logic that generates memory addresses that permit direct memory addressing of the control store and data store memories by way of the interface. A memory access controller (178) is coupled to the two address generators (170, 176) to control access to the respective data store and control store memories (13, 15) by the respective ad- dress generators. The memory access controller (178) comprises arbitration logic(180, 184) which arbitrates between requests for data store memory access and con- trol store memory access. The second address generator (176) comprises a cache memory (190) which stores sets of control parameters provided by the control store memory (15), which control parameters comprise segment, offset bias and word count data. An adder (198), which adds the offset and segment parameters to gener- ate a data store memory address, and decrementing logic (196) utilizes the count pa- rameter to determine the number of words to transfer to the data store memory. Asecond adder (194) combines the bias and offset parameters to provide a new offset which is stored in the cache memory (190).

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