Method and circuitry for aligning the phase of high-speed...

Details Method and circuitry for aligning the phase of high-speed... Method and circuitry for aligning the phase of high-speed...

H - Electricity

04

L

H04L 7/00 (2006.01) H04J 3/06 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2125113

METHOD AND CIRCUITRY FOR ALIGNING THE PHASE OF HIGH-SPEED CLOCKS IN TELECOMMUNICATIONS SYSTEMS ABSTRACT OF THE DISCLOSURE A method and circuitry are provided for detecting and measuring a phase difference between the output signals from a primary stratum clock and a standby stratum clock in a telecommunications system, computing a period of time needed for a numerically-controlled oscillator to shift the frequency of the standby clock enough to cancel the phase difference, transforming the required period of time into a signal representing a corresponding number of frequency shift steps, and controlling the numerically-controlled oscillator with the step signal to shift the frequency of the standby clock accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when either the system or user switches operations from the primary stratum clock module to the standby stratum clock module, phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

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