Synchronizing a data acquisition device with a host

Details Synchronizing a data acquisition device with a host Synchronizing a data acquisition device with a host

G - Physics

08

C

G08C 19/16 (2006.01) H03L 7/099 (2006.01) H04L 7/04 (2006.01) A61B 5/00 (2006.01) A61B 5/0408 (2006.01) H04L 7/00 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2241706

Apparatus for synchronizing a reference clock signal received from a host system with an A/D converter clock signal generated in a data acquisition pod. The pod includes a decoder responsive to communication received from the host for extracting a host reference signal, and a clock signal source for developing an A/D reference clock signal having a frequency that is different from the frequency of the host reference signal. The pod also includes an A/D converter and a pulse modifying digital phase-locked loop (PLL). The PLL is responsive to the A/D reference clock signal and the host reference signal for developing an A/D clock signal for the A/D converter in which one of its clock periods is periodically modified, thereby locking the rate at which the A/D converter develops samples to the rate at which the host system requests samples. In a preferred embodiment the pod also includes a signal detector for detecting a specified alignment in time of the readiness of the A/D converter to provide a given sample with a host system request for that given sample, and upon such detection, selectively providing an enable signal to the PLL, thereby enabling operation of the PLL and synchronizing the host and pod clock rates, as well as locking in a given alignment the providing to the host of the samples developed by the A/D converter with the host system requests for those samples.

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