Synchronous processing circuit

H - Electricity – 04 – N

Patent

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Details

H04N 5/06 (2006.01) H04N 5/08 (2006.01) H04N 5/10 (2006.01)

Patent

CA 2326326

With the present invention, asynchronous processor circuit can be implemented with a simplified circuit by improving a display's synchronization stability, and by setting a pulse width of a vertical synchronizing signal to be integral multiple of that of the frequency of the horizontal synchronizing signal. In a synchronous processor circuit in FIG. 1, an LPF 1 receives an externally provided composite signal 5, and a vertical synchronization separating signal 6 is separated therefrom; a 1/2 frequency divider circuit 4 outputs a vertical phase detection signal 9 obtained by dividing the frequency synchronization separating signal 6 into 1/2; a phase delay part 2 receives the composite signal 5 and outputs a plurality of horizontal synchronizing signals 19 to 24 each differently delayed in phase; and a vertical synchronizing signal reproduction circuit 3 uses the vertical synchronization separating signal 6 and the plurality of phase-delayed horizontal synchronizing signals 19 to 24 to output a vertical synchronizing signal 8 having the phase relationship determined with respect to the horizontal synchronizing signal.

Dans un circuit de traitement synchrone, un LPF (1) sépare un signal de séparation de synchronisation verticale (6) d'un signal composite (5) provenant de l'extérieur; un circuit de répartition en fréquence par moitié (4) produit un signal de détection de phase verticale (9) obtenu par répartition du signal de séparation de synchronisation verticale (6) par moitié; un circuit à retard de phase (2) dans lequel le signal composite (5) est entré produit une pluralité de différents signaux de synchronisation horizontale à retard de phase (19 à 24); et un circuit de reproduction (3) du signal de séparation de synchronisation verticale met en oeuvre le signal de séparation de synchronisation verticale (6) et la pluralité de signaux de synchronisation horizontale à retard de phase (19 à 24) pour produire un signal de synchronisation verticale (8) pour lequel un angle de phase comportant un signal de synchronisation horizontale est déterminé.

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