Video memory system with intermediate buffer

Details Video memory system with intermediate buffer Video memory system with intermediate buffer

G - Physics

06

F

354/236.2

G06F 3/14 (2006.01) G09G 1/16 (2006.01) G09G 5/39 (2006.01)

Patent

CA 2031625

ABSTRACT OF THE DISCLOSURE A video memory system is disclosed including a video memory, an intermediate buffer, a video display control unit (VDCU), and a video processing means. The intermediate buffer is disposed between an external CPU and the video memory to intercept the address, data, and read/write signals from the CPU. For read operations, the intermediate buffer relays the read and address signals to the video memory and the data read therefrom travels through the buffer to arrive at the CPU. For write operations, the intermediate buffer stores the address and data signals from the CPU. The data is later written into the video memory in response to a time slot reference signal.

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