Digital channelizer having efficient architecture for window...

Details Digital channelizer having efficient architecture for window... Digital channelizer having efficient architecture for window...

H - Electricity

04

L

H04L 25/14 (2006.01) H04L 5/06 (2006.01)

Patent

CA 2298862

The invention is a digital channelizer (100) and process which divides an input bandwidth into at least some of N channels. The digital channelizer includes an analog to digital converter (14) which encodes the input bandwidth into a serial digital data stream of data words; a demultiplexer (16), coupled to the analog to digital converter, which divides the serial digital data stream into the parallel data streams of data words; a window presum (102) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a discrete Fourier transform apparatus (26'), having N inputs coupled to the N outputs of the window presum, which performs a discrete Fourier transform on N inputs to produce an output of at least some of the N channels.

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