Methods and apparatus for reading a full-swing memory array

G - Physics – 11 – C

Patent

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G11C 7/10 (2006.01)

Patent

CA 2610901

Techniques for reducing power when reading a full-swing memory array are disclosed. The full-swing memory array includes a plurality of local bit lines and a global bit line. In order to reduce power consumption, a method of driving the global bit line includes the step of coupling the plurality of local bit lines to the global bit line through a plurality of tri-state devices. The method further includes the steps of generating a global select signal to enable one of the plurality of tri-state devices and selecting a corresponding local bit line to drive the output of the enabled tri-state device. In this way, the global bit line is statically driven so that consecutive reads of bits having the same value read over the global bit line do not result in transitioning the state of the global bit line.

L'invention concerne des techniques permettant de limiter la puissance lors de la lecture d'un réseau mémoire à demi-cycles complets. Ledit réseau mémoire comprend une pluralité de lignes de bits locale et une ligne de bits globale. Pour réduire la consommation de puissance, un procédé de commande de la ligne de bits globale consiste à coupler la pluralité de lignes de bits locales avec la ligne de bits globale via une pluralité de dispositifs à trois états; à générer un signal de sélection globale afin d'activer l'un des dispositifs à trois états de la pluralité et à sélectionner une ligne de bits locale correspondante afin de commander la sortie du dispositif activé à trois états. De ce fait, la ligne de bits globale est commandée statiquement de sorte que les lectures consécutives de bits présentant la même valeur de lecture sur la ligne de bits globale n'entraînent pas la transition de l'état de la ligne de bits globale.

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