H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/302 (2006.01) B24B 37/04 (2006.01) C25F 3/16 (2006.01) H01L 21/321 (2006.01) H01L 21/3213 (2006.01) H01L 21/461 (2006.01) H01L 21/4763 (2006.01) H01L 21/768 (2006.01) H01L 23/48 (2006.01) H01L 23/52 (2006.01)
Patent
CA 2456225
A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area.
L'invention concerne un procédé de planarisation et de polissage électrolytique d'une couche conductrice sur une structure à semi-conducteur qui consiste à former une couche diélectrique pourvue de zones évidées et non évidées sur la tranche à semi-conducteur. Une couche conductrice est formée sur la couche diélectrique afin de recouvrir les zones évidées et les zones non évidées. La surface de la couche conductrice est ensuite planarisée afin de réduire les variations de la topologie de surface. La couche conductrice planarisée est ensuite polie de manière électrolytique afin d'exposer la zone non évidée.
Chang Ru Kao
Wang Hui
Yao Xiang Yu
Yih Peihaur
Acm Research Inc.
Borden Ladner Gervais Llp
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