Flag-based high-speed i/o data transfer

Details Flag-based high-speed i/o data transfer Flag-based high-speed i/o data transfer

G - Physics

06

F

G06F 13/16 (2006.01) G06F 12/04 (2006.01) G09G 5/39 (2006.01)

Patent

CA 2140963

A memory address pointer that selects a memory location that is mapped to a video graphics circuit port is incremented only when all bytes in a memory location have been read from or written to by the host CPU. This does not depend on the order in which the host CPU reads or writes data bytes. Therefore a video controller that uses the present invention will work with 8 bit, 16 bit as well as high performance 32 bit input/output instructions.

Un pointeur d'adresse-mémoire qui choisit un emplacement mémoire mappé à un port de circuit vidéographique est incrémenté seulement lorsque tous les multiplets d'un emplacement mémoire ont été lus ou enregistrés par le CPU hôte, sans égard à l'ordre dans lequel le CPU hôte lit ou enregistre les multiplets. Par conséquent, un contrôleur vidéo utilisant la présente invention fonctionnera avec des instructions d'entrée/sortie 8 bits, 16 bits et haute performance 32 bits.

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