H - Electricity – 04 – B
Patent
H - Electricity
04
B
325/80
H04B 1/16 (2006.01) H04L 7/033 (2006.01)
Patent
CA 2010213
PHF 89.511 15.01.1990 ABSTRACT Method and arrangement for bit synchronization in a receiver for digital data transmission. The received short-length packets of bit pulses are first converted into normalized 1 or 0 samples at the rate nFb, where Fb is the bit rate and n a small even integer. The method further comprises, for each )sub)-packet of M bits, the following steps: a) storing the normalized samples according to a sequence matrix [B] having (n+1) row-sequences B1, ..., BA+1 and M columns; b) determining and storing a transition column matrix [T] having n rows obtained by adding modulo-2 pairs of adjacent sequences B1, ..., Bn+1; c) calculating two barycentre numbers m1 and m2 for the upper and lower half of the matrix [T]; d) calculating a barycentre number m of matrix [T] derived from numbers m1 and m2 and matrix [T] or matrix [T] robated cyclically by half the number of rows (n/2), depending on whether m2-m1 is smaller than n/2 or not. e, f) calculating an integer j=(m'-n/2) modulo-n, where m' is the nearest integer to number m ; g) choosing the sequence Bj as the optimum sequence representative of the M-bit (sub)-packet in question.
Fetherstonhaugh & Co.
Philips Electronics N.v.
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