Techniques for pin arrangements in circuit chips

Details Techniques for pin arrangements in circuit chips Techniques for pin arrangements in circuit chips

H - Electricity

01

L

H01L 23/50 (2006.01) H01L 23/498 (2006.01) H01L 23/485 (2006.01)

Patent

CA 2478906

Techniques for improved contact mapping in circuit devices are disclosed. In one particular exemplary embodiment, a technique may be realized as a circuit device comprising a circuit chip having a plurality of electrical contacts positioned at a surface of the circuit chip so as to form one or more channels at the surface, the one or more channels being substantially devoid of electrical contacts such that one or more corresponding channels are formed in a chip carrier for routing electrically conductive traces from one or more of the plurality of electrical contacts on a routing layer of the chip carrier.

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