H - Electricity – 03 – M
Patent
H - Electricity
03
M
H03M 13/11 (2006.01)
Patent
CA 2540892
A channel encoding apparatus using a parallel concatenated low density parity check (LDPC) code. A first LDPC encoder generates a first component LDPC code according to information bits received. An interleaver interleaves the information bits according to a predetermined interleaving rule. A second LDPC encoder generates a second component LDPC code according to the interleaved information bits. A controller performs a control operation such that the information bits, the first component LDPC code which is first parity bits corresponding to the information bits, and the second component LDPC code which is second parity bits corresponding to the information bits are combined according to a predetermined code rate.
L'invention concerne un appareil de codage de canal faisant appel à un code à contrôle de parité basse densité (LDPC) concaténé parallèle. Un premier codeur LDPC génère un premier code LDPC composant selon des bits d'information reçus. Un entrelaceur entrelace les bits d'information selon une règle d'entrelacement prédéterminée. Un second codeur LDPC génère un second code LDPC composant selon les bits d'information entrelacés. Un contrôleur réalise une opération de contrôle permettant de combiner les bits d'information, le premier code LDPC composant sous forme de premiers bits de parité correspondant aux bits d'information, et le second code LDPC composant sous forme de seconds bits de parité correspondant aux bits d'information, à un débit de code prédéterminé.
Jeong Hong-Sil
Kim Jae-Yoel
Kyung Gyu-Bum
Marks & Clerk
Samsung Electronics Co. Ltd.
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