Data and forward error control coding techniques for digital...

H - Electricity – 03 – M

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H03M 7/00 (2006.01) H04L 1/00 (2006.01) H04L 25/49 (2006.01)

Patent

CA 2021072

ABSTRACT OF THE DISCLOSURE An encoder encodes a plurality of bit sequences of a digital signal into data codewords having improved signal characteristics, i.e., limited maximum run lengths and limited cumulative DC-offsets. Then, the encoder performs error protection encoding on the data codewords using a forward error control ("FEC") code to form an FEC code block from a number of the data codewords. Preferably, the FEC code block is formed by generating a number of check or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword so that one FEC bit and its complement are interposed between each successive codeword. In a preferred embodiment, a 96-bit FEC code block is formed from eight 10-bit data codewords (formed by an 8b/10b data encoder), eight FEC bits, and eight FEC complement bits. In another preferred embodiment, each 16-bit input sequence is encoded into a 20-bit data codeword pair made up of a 9-bit codeword and an 11-bit codeword. An implementation of this embodiment uses a precoder and 8b/9b and 10b/11b sub-encoders, which collectively perform 16b/20b encoding. Then, an 8-bit FEC is generated from an 80-bit block consisting of four of the 20-bit codeword pairs. One FEC bit and its binary complement are concatenated to each 9-bit and 11-bit data codeword, resulting in a 96-bit FEC block. Preferably, the data codewords in the FEC blocks are 3/4/3 codewords. Also, the complementary FEC bit pairs can be used at the receiver to obtain proper framing of the FEC code block prior to decoding.

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