Clock recovery pll

H - Electricity – 04 – L

Patent

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Details

H04L 7/033 (2006.01) H03L 7/085 (2006.01) H03L 7/099 (2006.01) H04J 3/06 (2006.01) H04Q 11/04 (2006.01) H03L 7/087 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2328316

A multimode clock recovery circuit for providing constant bit rate services in a cell relay network has an embedded digital phase locked loop including an input circuit capable of generating a phase signal from at least two types of input signal. The phase signal controlling the output of the phase locked loop generates clock signals for the constant bit rate services.

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