Memory write protection method and apparatus

Details Memory write protection method and apparatus Memory write protection method and apparatus

G - Physics

06

F

G06F 11/00 (2006.01) G11C 7/00 (2006.01) G11C 7/22 (2006.01) G11C 7/24 (2006.01) G11C 16/04 (2006.01) G11C 16/06 (2006.01) G11C 29/00 (2006.01) H04Q 7/32 (2006.01)

Patent

CA 2097308

2097308 9307565 PCTABS00021 A write protection apparatus is disclosed. The write protection apparatus couples a data supplying device (121) to the data input of a memory device (127). The memory protection device generates a first signal (211) which triggers generation of a second signal (215). The second signal (215) is active for a first predetermined time and is coupled to the input of the memory device (127). At any time during this first predetermined time, a third signal (209) may be generated. The third signal (209) inactivates the second signal. This third signal (209) may be triggered by numerous events including: generation of a read signal, generation of a chip select signal, or indication that the end of the data to be written to the memory device (127) has occurred.

Affiliated with

Also associated with

Rating

Memory write protection method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory write protection method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory write protection method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1799332