Asynchronous digital system, asynchronous data path circuit,...

Details Asynchronous digital system, asynchronous data path circuit,... Asynchronous digital system, asynchronous data path circuit,...

H - Electricity

04

L

H04L 29/02 (2006.01) G06F 15/16 (2006.01) G06F 17/50 (2006.01) H04B 1/10 (2006.01)

Patent

CA 2217471

A asynchronous digital system, an asynchronous data path circuit, an asynchronous digital signal processing circuit and anasynchronous digital signal processing method, which enables improved processing speed while maintaining high reliability are provided by dividing the overall chip into blocks with a specified area, forming the connection between the blocks by applying thereto a delay insensitive (DI) model or a quasi delay insensitive (QDI) model, while forming each block by applying thereto a scalable delay insensitive (SDI) model. In the SDI model, the system is configured using circuit components having a delay assumed during design in which if the specification states that a signal transition (b) in a subcircuit 7 precedes a signal transition (c) in a subcircuit 8, k ~ Tab < Tac is established wherein Tab is the time from the occurrence of the signal transition (a) that is a common cause until the occurrence of the signal transition (b) and Tac is the time from the occurrence of the signal transition (a) until the occurrence of the signal transition (c)~ k is a constant that is defined to be a real number larger than 1.

Système numérique asynchrone, un circuit de trajet de données asynchrone, un circuit de traitement de signal numérique asynchrone et une méthode de traitement de signal numérique asynchrone, permettant une plus grande vitesse de traitement dans des conditions de grande fiabilité, l'ensemble de la puce étant divisé en blocs d'une certaine étendue reliés conformément à un modèle insensible aux retards (DI) ou à un quasi-modèle insensible aux retards (QDI) tout en étant formés chacun conformément à un modèle dimensionnable insensible aux retards (SDI). Suivant le modèle SDI, le système est configuré à l'aide de composants de circuit dont le retard est pris en compte lors de la conception de sorte que, si la spécification indique que la transition d'un signal (b) dans un sous-circuit 7 précède la transition d'un signal (c) dans un sous-circuit 8, k ~ Tab < Tac est établi, où Tab est l'intervalle de temps entre l'occurrence de la transition du signal (a) (cause commune) et l'occurrence de la transition du signal (b) et Tac est l'intervalle de temps entre l'occurrence de la transition du signal (a) et l'occurrence de la transition du signal (c) ~ k est une constante qui est définie comme un nombre réel supérieur à 1.

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