H - Electricity – 04 – L
Patent
H - Electricity
04
L
H04L 12/56 (2006.01) H04J 3/06 (2006.01)
Patent
CA 2118548
A frame aligner circuit for aligning a plurality of information packet signals received within a maximum starting time variation interval consists of a plurality of frame detectors, stretch circuits and variable delay circuits which are controlled by a synchronization signal generator and a delay control circuit. The delay control circuit in one embodiment of the present invention delays each information packet signal for a duration of time defined by the start of the information packet signal and an interval of time following the start of a last received information packet signals. In this manner, each information packet signal is delayed a corresponding period of time to align the plurality of information packet signals with respect to one another.
American Telephone And Telegraph Company
Kirby Eades Gale Baker
LandOfFree
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