Framing bit sequence detection in digital data communication...

Details Framing bit sequence detection in digital data communication... Framing bit sequence detection in digital data communication...

H - Electricity

04

L

H04L 7/00 (2006.01) H04J 3/06 (2006.01) H04L 7/10 (2006.01)

Patent

CA 2052811

In order to detect a plurality of framing bit sequences for establishing synchronization at a receiver in a digital communications system, first and second counters are rapidly reset in order to establish the synchronization as early as possible. A comparator receives a bit stream transmitted and a desired bit sequence for use in detecting the framing bit, and compares the desired bit sequence with part of the bit stream and issues a coincidence signal in the event that the desired bit sequence coincides with the part of the bit stream. The first counter is coupled to receive the coincidence signal, and allows an output indicating the establishment of the synchronization to issue in the event that it reaches a predetermined number of correct coincidence signals. The second counter counts up the number of occurrences of the output of a clock counter, and resets itself and the first counter when reaching a predetermine number of occurrences of a pseudo- coincidence signal.

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