Multi-layer tolerance checker

Details Multi-layer tolerance checker Multi-layer tolerance checker

G - Physics

01

R

G01R 31/28 (2006.01)

Patent

CA 2017865

Multi-layer printed circuit boards are sometimes connected to transmission paths which may be susceptible to electrical discharges associated with transient electrical events occurring along the transmission path. A method is provided for assuring that two respective layers of the printed circuit board are aligned within predetermined tolerances. Aligning respective layers within acceptable tolerances provides a means of assuring that predetermined distances between a ground layer and a power layer will be maintained, thereby ensuring that electrical arcing will not occur between the power and ground layer in the event of voltage spikes or current surges.

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