Procedure for reception end clock speed recovery for digital...

Details Procedure for reception end clock speed recovery for digital... Procedure for reception end clock speed recovery for digital...

H - Electricity

04

L

H04L 7/00 (2006.01) H04J 3/06 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2171933

In a procedure for the reception end clock speed recovery of digital signals with a constant bit rate after cell structured, asynchronous transmisslon with pauses of various lengths between individual cells, whlle using the occupancy status of a FIFO memory into which the digital signals that have been received are read in, at the start of a transmission, initially the digital signals with are read with a received clock speed into the plurality of cells of the FIFO memory that comprises the received signals, until such time as the FIFO memory is half-full. The digital signals that have been read into the FIFO memory are read out at a readout clock speed that is at a frequency that is lower than the frequency of the received clock speed. During the read out, a signal to control the frequency of the read out clock speed is derived from the particular occupancy status of the FIFO memory.

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