H - Electricity – 04 – N
Patent
H - Electricity
04
N
H04N 7/26 (2006.01) H04N 7/50 (2006.01)
Patent
CA 2522856
A transcoder architecture that provides the lowest possible complexity with a small error, e.g., for converting an MPEG-2 bitstream into an MPEG-4 bitstream. The transcoder reads header information (304) from an input bitstream and provides a corresponding header in the new format for the output bitstream. In one embodiment (Fig. 3), a low complexity front-to-back transcoder (with B frames disabled) avoids the need for motion compensation processing. In another embodiment (Fig. 4), a transcoder architecture that minimizes drift error (with B frames enabled) is provided. In another embodiment (Fig. 5), a size transcoder (with B frames enabled) is provided, e.g., to convert a bitstream of ITU-R 601 interlaced video coding with MPEG-2 MP@ ML into a simple profile MPEG-4 bitstream which Contains SIF progressive video suitable for a streaming video application. For spatial downscaling of field-mode DCT blocks, vertical and horizontal downscaling techniques are combined to use sparse matrixes to reduce computations.
Chen Xuemin
Panusopone Krit
General Instrument Corporation
Ridout & Maybee Llp
LandOfFree
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