Electronic component with output buffer control

Details Electronic component with output buffer control Electronic component with output buffer control

G - Physics

01

R

G01R 31/3185 (2006.01)

Patent

CA 2465608

According to the invention, the aim of an optimisation of the timing in normal mode with no disadvantage to, or limitation of the scanning mode may be achieved for an electronic component (1) with an integrated circuit (2) comprising output flip-flops (15), the output data of which in the normal mode of the component (1) is transmitted to an output buffer (16) on the component (1), controlled by a control signal, the control signal being provided in normal mode by an output-enable flip-flop (18) provided for the output buffer (16) and in a scan mode for the component by scan-enable cells (25). Said aim is achieved, whereby a device is provided, in which in the scan mode, a scan- enable cell (25) controls at least two output buffers (16).

L'invention concerne un composant électronique (1) doté d'un circuit intégré (2) qui présente des bascules bistables de sortie (15) dont les données de sortie sont respectivement retransmises à un tampon de sortie (16) du composant (1) lorsque le composant (1) est en mode de fonctionnement normal, ces bascules étant commandées par un signal de commande. Lorsque le composant est en mode de fonctionnement normal, le signal de commande est délivré par une bascule bistable d'activation de sortie (18) associée au tampon de sortie (16) et, lorsqu'il est en mode balayage, le signal de commande est délivré par les cellules d'activation de balayage (25). L'invention vise à optimiser, pour un tel composant, la synchronisation en mode normal sans inconvénient ni restriction pour le mode balayage. A cet effet, lorsque ce composant est en mode de balayage, une cellule d'activation de balayage (25) commande au moins deux tampons de sortie (16).

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