Multiple clock signal generation from a common oscillator

Details Multiple clock signal generation from a common oscillator Multiple clock signal generation from a common oscillator

G - Physics

01

S

G01S 19/13 (2010.01) G01S 19/03 (2010.01)

Patent

CA 2657988

A system and method of providing a clock signal to a navigation satellite receiver (266) in a device (100) is disclosed. A clock signal generated by a voltage controlled temperature compensated crystal oscillator (VCTCXO) (400) in a cellular engine (221) of the same device (100) is appropriated to clock a numerically controlled oscillator (NCO) (490) programmed to generate an adjusted clock signal (491) suitable for use in receiving signals from navigation satellites and to heterodyne them down to baseband or an intermediate frequency for processing. Preferably, if the cellular engine (221) has an automatic frequency control (AFC) module (466) for adjusting the voltage control (464) input to the VCTCXO (400) to compensate for a change in the operating environment of the cellular engine (221), the AFC module (466) modifies the control word (501) in the NCO (490) to counteract such adjustment so that the adjusted clock signal (491) provided to the navigation satellite receiver is not unduly impacted. The use of the NCO (490) ensures that the adjusted clock signal (491) remains phase continuous throughout any such adjustments, so that positional lock of the navigation satellite receiver (266) should not be lost. The sharing of the VCTCXO (400) by the cellular engine (221) and the navigation satellite receiver (266) results in component cost and board space savings, economy in power consumption and reduced engineering effort in routing clock signals throughout the circuit board.

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