Burst demodulator for establishing carrier and clock timing...

Details Burst demodulator for establishing carrier and clock timing... Burst demodulator for establishing carrier and clock timing...

H - Electricity

03

D

329/3

H03D 3/18 (2006.01) H04L 27/38 (2006.01) H04L 7/04 (2006.01)

Patent

CA 2018855

- 27 - ABSTRACT OF THE DISCLOSURE In a burst demodulator, an APSK burst signal containing a preamble of alternating "1" and "-1" symbols, followed by a data field is received and quasi-coherently demodulated into a baseband complex signal, which is converted to digital form such that each symbol of the complex signal yields N digital samples, with N being selected such that at least one of the N digital samples is closest to a signal point of the burst signal. A clock recovery circuit is responsive to the arrival of the burst for estimating the symbol timing of the burst signal from digital samples of the preamble. A digital sample is extracted from every N samples of the preamble in response to the estimated symbol timing so that it is most likely to be closest to the signal point. A carrier recovery circuit responds to the estimated symbol timing by estimating the carrier frequency and phase of the burst signal from the extracted digital samples to produce a complex carrier signal, which is multiplied with the extracted digital samples to recover the original signal. Memories are preferably provided to store the received burst signal. By repeatedly reading the preamble from the memories, the same symbols of the preamble can be used for clock timing and carrier phase recovery operations.

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