G - Physics – 06 – F
Patent
G - Physics
06
F
354/222
G06F 11/00 (2006.01) H04L 27/18 (2006.01)
Patent
CA 2038472
An error suppression system suppresses an error of a data sequence generated in a transmission path between a transmitting terminal and a receiving terminal. The error suppression system includes a data coding circuit in the transmitting terminal for inserting a known bit at a predetermined position of the data sequence and for carrying out a difference logic conversion with respect to the data sequence, a differential coding circuit in the transmitting terminal for carrying out a sum logic conversion with respect to the data sequence which is received from the data coding circuit, a differential decoding circuit in the receiving terminal for carrying out a difference logic conversion with respect to the data sequence received from the differential coding circuit via the transmission path, and a data decoding circuit in the receiving terminal for carrying out a sum logic conversion with respect to the data sequence received from the differential decoding circuit and for restoring the known bit at the predetermined position of the data sequence.
Fetherstonhaugh & Co.
Fujitsu Limited
LandOfFree
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