Memory emulation test system in which undesirable...

Details Memory emulation test system in which undesirable... Memory emulation test system in which undesirable...

G - Physics

06

F

G06F 11/00 (2006.01) G01R 31/28 (2006.01) G06F 11/26 (2006.01)

Patent

CA 2047624

MEMORY EMULATION TEST SYSTEM IN WHICH UNDESIRABLE MICROPROCESSOR RESET IS PRECLUDED Abstract of the Disclosure An emulative test system is provided in which a UUT microprocessor may execute user-written code in an emulation memory, or pre-existing code in a UUT boot ROM, at its own clock rate, and then switch to execution of tester-supplied code from the test system's emulation memory without resetting the UUT microprocessor or disturbing UUT devices that have been initialized.

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