System and method for inter-processor communication

G - Physics – 06 – F

Patent

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G06F 15/163 (2006.01) G06F 1/04 (2006.01) H04L 12/40 (2006.01) H04L 29/08 (2006.01)

Patent

CA 2701205

A means for reliable inter-processor communication in a multi-processor system is described. In accordance with one aspect, a specially-configured serial bus is used as a general-purpose data link between a first processor and a second processor. The serial bus may be an Inter-IC Sound (I2S) bus. In accordance with another aspect, a network interface residing on a second processor is made available to a first processor via a data link established over an I2S bus. This allows the second processor to be used as a proxy and to support remote configuration and network address traversal.

L'invention concerne un moyen pour une communication interprocesseur fiable dans un système à plusieurs processeurs. Selon un premier aspect, un bus série configuré spécialement est utilisé en tant que liaison de données universelle entre un premier processeur et un second processeur. Le bus série peut être un bus I2S (Inter-IC Sound). Selon un autre aspect, une interface réseau résidant sur un second processeur est rendue accessible à un premier processeur via une liaison de données établie sur un bus I2S. Ceci permet l'utilisation du second processeur en tant que proxy et autorise la configuration à distance et la traduction d'adresses réseau.

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