Dual-path computer interconnect system with four-ported...

Details Dual-path computer interconnect system with four-ported... Dual-path computer interconnect system with four-ported...

G - Physics

06

F

354/233

G06F 13/14 (2006.01) G06F 15/173 (2006.01) H04L 12/56 (2006.01) H04L 12/44 (2006.01)

Patent

CA 2011935

DUAL-PATH COMPUTER INTERCONNECT SYSTEM WITH FOUR-PORTED PACKET MEMORY CONTROL ABSTRACT OF THE DISCLOSURE A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol. Packets of data are transferred between the system bus of the CPU and the packetmemory by a pair of data movers, one for read and one for write. The packet memory is accessed upon demand by the serial link, the port processor and the data movers, using interleaved cycles. To accommodate this access upon demand withoutrequest/grant cycles, parking registers are provided to store read or write data until a later cycle, and the data rate on the packet memory port is high enough to allow ample time for simultaneous use of both channels as well as packet processing and moving to and from the CPU.

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