Multi-port ethernet frame switch

Details Multi-port ethernet frame switch Multi-port ethernet frame switch

H - Electricity

04

L

H04L 12/56 (2006.01) H04L 12/02 (2006.01) H04L 12/26 (2006.01)

Patent

CA 2233276

An Ethernet switch which includes a plurality of medium access control (MAC) interface logic circuits each coupled to an associated output port operative to perform serial-to-parallel conversion for frames being received from an associated output port and parallel-to-serial conversion for frames being transferred to an associated output port and other interfacing functions. The switch has an internal bus, a buffer memory coupled to each of the MAC interface logic circuits at one end and to the internal bus at another end, a switch central processor coupled to the internal bus and a multi-channel Direct Memory Access (DMA) Controller coupled to the internal bus and to the switch central processor, operative to transfer incoming frames to an external memory and to transfer frames stored temporarily in external memory to their destination in accordance with instructions from the switch central processor. An external memory controller is coupled to the DMA Controller and to an external memory port. An expansion bus interface logic circuit is coupled to said DMA Controller and to an expansion bus port. The switch central processor performs frame address handling and controls transfer of incoming frames to their destination.

Commutateur Ethernet comprenant un certain nombre de circuits logiques d'interface MAC (commande d'accès au support), chacun étant couplé à un port de sortie associé permettant la conversion série-parallèle des trames reçues du port de sortie associé et la conversion parallèle-série des trames transférées au port de sortie associé ainsi que d'autres fonctions d'interface. Le commutateur a un bus interne, une mémoire tampon couplée d'un côté à chacun des circuits logiques d'interface MAC et, de l'autre, au bus interne, un processeur central de commutation couplé au bus interne et un contrôleur DMA (accès direct en mémoire) multicanal couplé au bus interne et au processeur central de commutation, permettant de transférer les trames d'arrivée à une mémoire externe et de transférer les trames stockées temporairement en mémoire externe à leur destination conformément aux instructions du processeur central de commutation. Un contrôleur de mémoire externe est couplé au contrôleur DMA et à un port de mémoire externe. Un circuit logique d'interface de bus d'extension est couplé audit contrôleur DMA et à un port de bus d'extension. Le processeur central de commutation assure le traitement des adresses de trame et commande le transfert des trames d'arrivée à leur destination.

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