Semiconductor structures and manufacturing methods

Details Semiconductor structures and manufacturing methods Semiconductor structures and manufacturing methods

H - Electricity

01

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356/128, 356/177

H01L 21/302 (2006.01) H01L 21/033 (2006.01) H01L 21/336 (2006.01) H01L 29/10 (2006.01) H01L 29/423 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1138571

Abstract of the Disclosure A semiconductor structure wherein a masking layer is formed to coves a portion of a surface of a semiconductor. A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with the masking layer, reducing the area of the making layer covering the semiconductor exposing a second different portion of the semiconductor contiguous to the first exposed portion of the semiconductor. Particles capable of establishing a doped region in the semiconductor layer are introduced into the second, different exposed portion of the semiconductor to form a second doped region in the semi- conductor contiguous to the first doped region, such chemically etched masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self-aligned gate region may be formed in a field effect device having small channel lengths.

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