G - Physics – 06 – F
Patent
G - Physics
06
F
340/84
G06F 15/16 (2006.01) G06F 13/36 (2006.01) G06F 15/17 (2006.01)
Patent
CA 1113572
Abstract of Disclosure: The invention relates to an arrangement in a computer system for transmitting signals from one processor to one or several other processors connected to the same bus system, so that the signals having priority are trans- mitted without time delay and that the sequence of sig- nals without priority is not changed, each processor con- taining a sender buffer for sending all the signals and a queue buffer for storing signals without priority. If signals having no priority prevent signals having pri- ority from being transmitted through the bus system because of congestion in the receiving equipment, the arrangement allows said signal having no priority to move from the sender buffer to the first place in said queue buffer. The arrangement includes detecting means which activate a logical circuit when the folowing conditions are fulfilled: a the sender buffer is occupied b there is congestion in the receiving device c the signal in the sender buffer is a signal without priority d a signal having priority is to be fed into the sender buffer When the logical circuit is activated it delivers an out- put to a control signal circuit which, when activated, produces a signal on a first output and with a slight time delay produces a signal on a second output. The first of said output signals activates gate circuits for moving the contents of the sender buffer into the first place in the queue buffer. The second of said output signals activates a gate circuit for feeding the signal having priority into the sender buffer.
297919
Eklund Mats F.
Kjoller Hans O.
Nyman Anders B.j.
Marks & Clerk
Telefonaktiebolaget Lm Ericsson
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