First in first out activity queue for a cache store

Details First in first out activity queue for a cache store First in first out activity queue for a cache store

G - Physics

06

F

354/246

G06F 15/16 (2006.01) G06F 12/08 (2006.01) G06F 12/12 (2006.01) F02B 75/02 (2006.01)

Patent

CA 1123519

ABSTRACT A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system, a high speed buffer cache store, a central processor unit (CPU) and an Input/Output processor (IOP). Apparatus in the cache store reads all information on the system bus into a first in, first out buffer comprising a plurality of registers, a write address counter, a read address counter and a means for selectively processing the information. -2-

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