Semiconductor capacitor structure and memory cell and method...

Details Semiconductor capacitor structure and memory cell and method... Semiconductor capacitor structure and memory cell and method...

G - Physics

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G11C 11/24 (2006.01) G11C 11/35 (2006.01) G11C 11/404 (2006.01) H01L 27/07 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1059628

SEMICONDUCTOR CAPACITOR STRUCTURE AND MEMORY CELL AND METHOD OF MAKING Abstract of the Disclosure In one example, a random access memory cell includes an MOS gating transistor to activate the cell for reading writing, or refreshing data stored on a cell capacitor structure. A typical cell transistor includes P1 (input/ output) and P2 (cell storage) diffusions in an N-type sub- strate, P2 serving as one terminal or plate of the cell capacitor structure. According to this application, a preferred cell capacitor is formed by diffusing an N+ region over a major portion of the P2 region and extending beyond the P2 region in electrical contact with the grounded N substrate. The primary cell capacitor is defined between the P2 diffusion, a depletion region induced at the P2-N+ junction when P2 is charged, and the grounded N substrate. The N+ diffusion also reduces an unwanted parasitic capacitance between the P2 region and a transistor gate conductor for the cell, reduces leakage currents and permits greater packing density of cells. More generally, the application relates to an improved semiconductor capacitor storage structure and method, including a substrate of one conductivity type, a first diffusion of the opposite type on the substrate and constituting one capacitor terminal, and a second diffusion of the substrate conductivity type covering most of the first diffusion and in electrical contact with the substrate, the second diffusion and substrate forming the second capacitor terminal. The dielectric of the capacitor storage structure is formed by a depletion region between the first diffusion and both the substrate and second diffusion. -1-

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