Memory refresh for high speed compact digital computer system

Details Memory refresh for high speed compact digital computer system Memory refresh for high speed compact digital computer system

G - Physics

06

F

354/237

G06F 13/00 (2006.01)

Patent

CA 1143858

ABSTRACT Therein is disclosed high speed, compact computer system architecture. System architecture includes a processor for processing machine language data, a memory for storing at least machine language instructions for use by processor, microinstruc- tion logic for storing and providing sequences of frequently used instructions, and busses for transmitting at least instructions between processor and memory. Microinstruction memory circuitry is disclosed for efficient storage of microinstructions in available microinstruction memory space. Also disclosed is microinstruction selection circuitry for high speed selection of successive micro- instructions of a sequence. Memory control circuitry is disclosed for providing memory refresh during battery back-up operation, preventing loss of user program and data stored in memory.

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