Method of producing relief structures for integrated...

Details Method of producing relief structures for integrated... Method of producing relief structures for integrated...

H - Electricity

01

L

356/136

H01L 21/42 (2006.01) G03F 7/09 (2006.01) H01L 21/312 (2006.01)

Patent

CA 1165466

ABSTRACT OF THE DISCLOSURE Relief structures comprised of double lacquer layers on substrates already having relief structures for integrated semiconductor circuits are produced by applying a lower lacquer layer onto such substrate and which is composed of a material which does not cross-link or decompose due to radia- tion energy and which has only relatively slight sensitivity at the radiation energy dosage range utilized for structuring; applying an upper lacquer layer onto the lower lacquer layer and which upper layer is thinner relative to the thickness of the lower layer by a factor of at least 2 and is composed of a highly sensitive negative lacquer material; generating desired relief structures in the upper lacquer layer and removing those portions of the lower lacquer layer which are not covered by the upper negative lacquer layer.

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