Soft error rewrite control system

Details Soft error rewrite control system Soft error rewrite control system

G - Physics

11

C

354/224, 352/81

G11C 29/00 (2006.01) G06F 11/00 (2006.01) G06F 11/14 (2006.01) G06F 11/22 (2006.01) G11C 11/406 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1168364

ABSTRACT OF THE DISCLOSURE Refresh and initialize counter circuits included within a dynamic memory system are supplemented with addi- tional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with modulus one less than a maximum count so as to generate a sequence of counts over a corre- sponding number of cycles of operation for selection of row and column addresses which enable the information stored in each location of the memory system to be read out, corrected for single bit errors and rewritten back thereby rendering the system less susceptible to soft errors such as those produced by alpha particles.

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