Logic circuit in 2-phase mos-technology

H - Electricity – 03 – K

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H03K 19/094 (2006.01) H03K 19/017 (2006.01) H03K 19/0185 (2006.01) H03K 19/096 (2006.01)

Patent

CA 1180063

PHD 80 179 16 ABSTRACT: In a logic circuit arrangement comprising a plurality of sticks formed by series arrangements of transistors which receive the signals to be processed a conductive stick not only has to discharge the output capacitance of the logic output but also other sticks which are not completely conductive, namely up to the first cut-off transistor. This may result in a very high capacitive load, which substantially reduces the maximum attainable switching speed. In accordance with the inven- tion an additional transistor is arranged between each stick and the output of the entire logic circuit, which transistor receives a gate voltage such that current flow from the cut-off charge sticks via a conductive stick is prevented or delayed until the output signal of the logic circuit has assumed a value which umambiguously switches over the next output transistor. As a result of this, a conductive stick only has to discharge the output capaci- tance of the logic circuit arrangement, so that a sub- stantially higher switching speed can be obtained.

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