Computer memory controller

G - Physics – 06 – F

Patent

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Details

G06F 1/30 (2006.01) G11C 11/406 (2006.01)

Patent

CA 2241126

A computer memory controller comprises a DRAM timing control section that provides, during memory back-up operation mode, self-refresh timing to DRAM array having self-refresh function. It also comprises a refresh/back-up control section that provides information as to memory back-up state to the DRAM timing control section. A DRAM identification mode register is provided. When DRAM array without self-refresh function is mounted, the state of the register changes. The state of the register is fed to the DRAM timing control section, thereby to provide timing according to the conventional CBR refresh method to the DRAM array.

L'invention est un contrôleur de mémoire d'ordinateur comprenant une unité de commande de synchronisation de DRAM qui, en mode de sauvegarde, fournit un signal d'autorégénération à un réseau de DRAM doté d'une fonction d'autorégénération. Le contrôleur de l'invention comprend également une unité de commande de régénération/sauvegarde qui fournit des informations sur l'état de la sauvegarde à l'unité de commande de synchronisation des DRAM. Un registre à modes d'identification des DRAM est intégré au contrôleur. Quand un réseau de DRAM sans fonction d'autorégénération est installé, l'état du registre est modifié. Cet état est transmis à l'unité de commande de synchronisation des DRAM , ce qui permet de réaliser dans le réseau de DRAM une synchronisation conforme à la méthode de régénération CBR courante.

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