Dual interleaved output queue

Details Dual interleaved output queue Dual interleaved output queue

G - Physics

06

F

G06F 13/00 (2006.01) G06F 15/17 (2006.01)

Patent

CA 2045063

An interleaved output queue is used as a high performance interface on a system bus for transferring information from a CPU to main memory. The queue is loaded on its input side with information that is bound for transmission from the CPU's cache to main memory. On its output side, the queue is unloaded by dual sets of unload circuitry, each of which accesses the information stored in either the odd or even queue entry addresses. Other select circuitry will alternate the transmission of information out of the two sets of unload circuitry to main memory. Each set of unload circuitry receives error information back from main memory during the time that the other unload circuitry is issuing a transaction. Transactions issued from the queue can proceed in an immediately successive sequence without waiting for the processing of error information from the immediately preceding transaction yet the queue can still recover form errors during high performance operation.

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