A bus interface for cell and/or packet data transfer

Details A bus interface for cell and/or packet data transfer A bus interface for cell and/or packet data transfer

H - Electricity

04

L

H04L 29/10 (2006.01) H04L 12/403 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2313087

This document discloses some technical details of a FIFO interface used for both cell and packet data transfer. This interface is suitable for a large number of ports. It operates at an overall throughput of 800 Mb/s for 16-bit wide data paths at 50 MHz, and 3.2 Gb/s for 32-bit wide data paths at 100 MHz. It is designed to have minimal compatibility issues with UTOPIA L2 and similar interfaces.

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