H - Electricity – 03 – K
Patent
H - Electricity
03
K
H03K 19/0175 (2006.01) H03K 19/017 (2006.01)
Patent
CA 2062414
An interconnection circuit has a first circuit portion in one of two integrated semiconductor circuits to be connected, for limiting the amplitude involtage of the signal output from the one circuit, and has a second circuit portion in the other one of the two circuits, for discriminating the logic level of the signal input thereinto based on a threshold level set at a level intermediate of the limited amplitude. The amplitude of the logic signal transferred between the two circuits is thus compressed, thereby decreasing a delay time for the signal to transfer between the two circuits.
L'invention est un circuit d'interconnexion comportant une première partie dans l'un de deux circuits intégrés à connecter pour limiter l'amplitude de la tension du signal de sortie de ce circuit, et une seconde partie dans l'autre des deux circuits pour soumettre le niveau logique de son signal d'entrée à une discrimination basée sur un seuil établi à un niveau intermédiaire de l'amplitude limitée. L'amplitude du signal logique transmis entre les deux circuits est ainsi comprimée, ce qui réduit le temps de transfert du signal entre les deux circuits.
Aoki Yasushi
Chiba Kiyohiko
Daikoku Shizue
Horita Satomi
Okamoto Hiroshi
Corporation Nec
G. Ronald Bell & Associates
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