A differential bipolar stray-insensitive pipelined...

Details A differential bipolar stray-insensitive pipelined... A differential bipolar stray-insensitive pipelined...

H - Electricity

03

M

H03M 1/66 (2006.01) H03M 1/06 (2006.01) H03M 1/72 (2006.01)

Patent

CA 2327644

Stray-insensitive pipelined Digital-to-Analog Convert- ers (DACs) can be implemented without an opamp in each stage. The quasi-passive circuit designed in this method dissipates less power, runs faster, has better ac- curacy, and takes less area than the conventional stray- insensitive architecture. A pipelined DAC designed with a differential bipolar architecture achieves close to 13 bits of linearity at 17.664 MSps conversion rate, which makes it suitable for full-rate downstream DSL signals. The converter is designed in a 0.6-µ double-poly CMOS tech- nology and dissipates 43 mW.

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