A high speed dram architecture with uniform access latency

Details A high speed dram architecture with uniform access latency A high speed dram architecture with uniform access latency

G - Physics

11

C

G11C 11/406 (2006.01) G11C 7/10 (2006.01) G11C 7/22 (2006.01) G11C 11/4076 (2006.01)

Patent

CA 2414920

A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

L'invention concerne une mémoire à accès aléatoire dynamique (DRAM) qui lit, écrit et met à jour les opérations. La DRAM est composée de plusieurs sous-réseaux, chacun d'eux possédant plusieurs cellules de mémorisation. Chacune d'elles est couplée avec un paire de canal bit et un canal mots complémentaire. La DRAM comprend également un dispositif d'activation du canal mots permettant de réaliser l'assertion d'un des canaux mots sélectionné et un dispositif de sélection de colonne pour réaliser l'assertion d'une paire de canaux de bit sélectionnée. Un circuit de synchronisation permet de commander le dispositif d'activation du canal mots, le dispositif de sélection de colonne et les opérations de lecture, écriture et mise à jour en réaction à une impulsion de synchronisation du canal mots. Les opérations de lecture, écriture et mise à jour sont réalisées simultanément.

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