A method for minimizing the critical dimension growth of a...

Details A method for minimizing the critical dimension growth of a... A method for minimizing the critical dimension growth of a...

H - Electricity

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L

H01L 21/302 (2006.01) H01L 21/3065 (2006.01) H01L 21/311 (2006.01) H01L 21/3213 (2006.01)

Patent

CA 2310057

A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor (20) and controlling the temperature of the wafer (26) by controlling the pressure of the gas contacting the backside of the wafer (26) and/or providing a heat source (56) such as for example in the chuck (46) or electrode (28) associated with the wafer (26) in order to heat the wafer (26).

Cette technique permettant de réduire au maximum la croissance de la dimension critique d'un élément sur une tranche de semiconducteur consiste à effectuer une attaque dans un réacteur (20) et à agir sur la température de la tranche (26) en commandant la pression du gaz entrant en contact avec l'envers de la tranche (26) et/ou à constituer une source de chaleur (56) dans le support (46) ou l'électrode (28) associés à la tranche (26) et ce, afin de la chauffer.

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