H - Electricity – 03 – M
Patent
H - Electricity
03
M
354/226, 354/67,
H03M 13/00 (2006.01) H03M 13/19 (2006.01)
Patent
CA 1314998
Abstract An apparatus which corrects single bit errors and detects double bit errors is presented. The present invention includes an encoder/decoder. During encoding the encoder/decoder produces a plurality of parity bits. These parity bits allow the correction of single bit errors in transmission and the detectionof double bit errors in transmission. The encoder/decoder comprises a plurality of arrays. Each array consists of logic gates arranged in the form of binary tree. Each array generates a single parity bit. Further every array receives as input the same number of data bits; however, each array receives a unique combination of data bits. When the encoder/decoder is used in decoding, the encoder/decoder produces a plurality of syndrome bits. These syndrome bits are used to correct single bit errors in transmission and to detect double bit errors in transmission. When decoding, each array of logic gates within the encoder/decoder produces a single syndrome bit. Each array has as input data bits, as when it is encoding. Additionally each array receives as input one and only one parity bit. The receipt of one and only one parity bit by each array allows for the encoder/decoder to be used both for encoding and decoding. This allows a great reduction in hardware required to implement error correction and detection.
578735
Hewlett-Packard Company
Sim & Mcburney
LandOfFree
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