Bicmos process having narrow bipolar emitter and implanted...

Details Bicmos process having narrow bipolar emitter and implanted... Bicmos process having narrow bipolar emitter and implanted...

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H01L 21/383 (2006.01) H01L 21/285 (2006.01) H01L 21/425 (2006.01) H01L 21/74 (2006.01) H01L 21/761 (2006.01) H01L 21/8249 (2006.01)

Patent

CA 1267444

BiCMOS PROCESS HAVING NARROW BIPOLAR EMITTER AND IMPLANTED ALUMINUM ISOLATION ABSTRACT OF THE DISCLOSURE A bipolar/CMOS process includes bipolar transistors having emitters formed in less than a minimal masking dimension. An opening is formed through a polycrystalline silicon layer deposited on a silicon substrate. After coating the sides of the opening with silicon dioxide, the intrinsic base region of the bipolar transistor and the emitter region are implanted. The extrinsic base is formed by out diffusion from the polycrystalline silicon layer. The structure includes an expitaxial layer which is more strongly doped below its surface than at its surface to enhance the performance of CMOS transistors formed therein. Additionally, the bipolar and complementary MOS transis- tors are self-aligned to each other by the manner in which the buried layers are formed.

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