Bus master with antilockup and no idle bus cycles

Details Bus master with antilockup and no idle bus cycles Bus master with antilockup and no idle bus cycles

G - Physics

06

F

G06F 12/00 (2006.01) G06F 13/16 (2006.01) G06F 13/30 (2006.01) G06F 13/368 (2006.01)

Patent

CA 2051177

Bus master for use in computer system includes logic for determining the number of words remaining to be transferred in a DMA operation to supply signals to permit arbitration to start for the next DMA request, thereby avoiding an idle cycle. A timeout state machine is also included to prevent the bus master state machine from hanging in a state with no exit. Errors can be masked to permit analysis of system problems.

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