Cache architecture for high speed memory-to-i/o data transfers

Details Cache architecture for high speed memory-to-i/o data transfers Cache architecture for high speed memory-to-i/o data transfers

G - Physics

06

F

G06F 13/20 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2103767

ABSTRACT CACHE ARCHITECTURE FOR HIGH SPEED MEMORY-TO-I/O DATA TRANSFERS Computer architecture and method of control for accomplishing low speed memory to high speed I/O data transfers. An I/O cache is connected between the memory data bus and a system I/O data bus, and is responsive to a storage control unit which manages data transfers over the system I/O bus. The relatively lower speed of the system memory is offset by the larger size of the memory data bus in comparison to the system I/O data bus. The I/O cache is used to prefetch memory data during read cycles, which prefetch operates in concurrence with the transfer of previously prefetched data from the I/o cache to I/O control units on the system I/O data bus. During the writing of data from I/O to system memory, the I/O cache buffers memory access interferences initiated by the processor. The invention permits the use of a conventional and relatively slow main memory in conjunction with a high speed processor and high speed I/O system.

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