Cache invalidate protocol for digital data processing system

Details Cache invalidate protocol for digital data processing system Cache invalidate protocol for digital data processing system

G - Physics

06

F

354/244

G06F 12/08 (2006.01)

Patent

CA 1296106

ABSTRACT OF THE DISCLOSURE A mechanism for determining when the contents of a block in a cache memory have been rendered stale by DMA activity external to a processor and for marking the block stale in response to a positive determination. The commanding unit in the DMA transfer, prior to transmitting an address, asserts a cache control signal which conditions the processor to receive the address and determine whether there is a correpondence to the contents of the cache. If there is a correspondence, the processor marks the contents of that cache location for which there is a correspondence stale.

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