G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.72
G06F 7/00 (2006.01) G06F 9/30 (2006.01) G06F 9/318 (2006.01)
Patent
CA 1186801
- 1 - Abstract: A central processing unit for use in an electronic system is designed for executing instructions of variable length in which an operand specifier, i.e. an instruction for specifying the addressing mode of an operand, is independent of an operation code for determining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing car be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
410221
Bandoh Tadaaki
Fukunaga Yasushi
Hiraoka Ryosei
Hirasawa Kotaro
Ide Jushi
Hitachi Ltd.
Kirby Eades Gale Baker
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